Trend of CMOS downsizing and its reliability
نویسندگان
چکیده
In this paper, CMOS downsizing trend into sub-70 nm node and further below is described. Downscaling of advanced CMOS devices have been significantly accelerated every time by the update of the ITRS roadmap. Now, on one hand, we can expect the realization of even sub-10 nm CMOS devices, but on the other hand, so many difficulties in technology for the downsizing are anticipated. In this paper, the difficulties and possible solutions are explained.
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ورودعنوان ژورنال:
- Microelectronics Reliability
دوره 42 شماره
صفحات -
تاریخ انتشار 2002